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Port assignment

The internal architecture:

Receiving path:

Packets from DIF are built in dif_port → rx_manager module. The ASIC packet from DIF has in principle 2.5 kB, but the DIF sends those packets cut into 100bytes. Those small packets are merged into a single packet in the BRAM and information about the packet is sent to a rx_queue. Packets are stored to the BRAM in a circular way, so the new packet is overwriting the old ones. The rx_queue concentrates information about all packets from all ports: the length of the packets, where in the BRAM the packet actually is and other information. The dif_port has typically a memory for  few big packets (corresponds to ~1.7 HBU). The queue has a size of 512 packet headers.

mem_man_axis → mem_man_axis_rx is collecting the packets from the BRAMS of all HDMI ports (dif_ports), adds a header (Packets#Header), trims to the proper length on the AXI4-Stream bus (using tkeeb signal) and sends the packet out. The end of the packet is marked with tlast=1. The memory manager has a large fifo: ~256 kB.

Timestamping module stores timestamp of internal events. can store ~2.5k timestamps. The  FIFO output directly is AXI4-Stream

Streams of timestamps and DIF packetsare merged via standard  AXI4-Stream interconnect, with an arbitration priority given to the timestamps packets. 

axi_merge_fifo sends the data directly to the DMA IP (not shown on picture). THe performance of DMA is much higher, when it treats larger packets instead of small packets

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