The latest generation of the DIF is called DIF2.
It uses a zynq SOC 7020. At the moment the processor part is used only to download the firmware from the flash and then goes to sleep.
The communication interface is either HDMI or USB. The firmware listens to both interface, but sends the answers only to the interface, from which it received the data last time.
Development software tool: Vivado 2015.4 + Xilinx SDK 2015.4. The Only reason for staying in this version is the CPU integration. The procedure to put the CPU into sleep (thus saving ~300 mA of current) does not directly work at the newer Vivado version.
Building the firmware
How to setup the Vivado project: look at the script at https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/dif2_fw/trunk/scripts/make_project.tcl . Modification of paths are needed before a direct use.
A generic guide how to setup a bootloader project in SDK a boot without a DDR: pdf.
For successful sleep (and therefore lower power consumption), copy the files from "sdk/" subdirectory in the sdk project before the final compilation. Those files also contain all the modification described in the pdf.
when the SDK is started from the Vivado for the second time, a different name of project is used. Files from svn (from sdk directory) have already fixed names. To start from scratch, delete the *.sdk directory from the vivado project directory and export hardware (including bitstream) again from vivado.
Flashing the Firmware
Flashing of the firmware is done from the xilinx sdk 2015.4.
1) Launch the SDK (unless already open from the building stage). Use any DIF2 project - the project is just needed to set up a correct FPGA type etc. (example project: https://www.desy.de/~kvas/DIF2/dif2_Two_SLABS_2015.4.tgz)
2) Invoke menu Xilinx tools → Program Flash. Change the path the the bitstream binary (*.bin file) and press program
The newer SDK (2019.1 tested) also requires the fsbl to be loaded. In that case, use the one from the xsdk project: fsbl/Debug/fsbl.elf
After a fresh SDK start, the programming over cable wont success. Look at the result message and just try again. There might be another (easier) method how to program the flash, but Jiri didn't find one.
TODO updating from command line:
Until the migration to git will be finished, the web svn links are not available. The svn files are accessible:
- Jiri's mirror: www.desy.de/~kvas/DIF2
from command line:
- branches/Retiming: the latest version for the ILC mode
- Trunk: https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/dif2_fw/trunk/
the last, up-to-date firmware, that has been used in the testbeam
- DutyCycle: https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/dif2_fw/branches/DutyCycle/
for huge layer with big power consumption: forced duty cycle
- ILC mode: https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/dif2_fw/branches/ILC_mode/
an older firmware and ILC-like timing of BXID of 200 ns
- Operation and Instruction Manual for the AHCAL elcetronics (TODO Mathias)
- DIF2 manual (TODO)
- DIF2 schematic (Mathias)
- CIB schematic (Mathias)
- HBU schematic (Mathias)
- Commands and packets