The LDA hardware was designed and manufactured in Mainz. There are two form factors of the LDA:

  1. mini-LDA: 10-ports mezzanine on Zedboard
  2. wing-LDA: 48-port fully custom board with more powerful FPGAs

Functional description

The common functionalities of both LDAs:

  • use clock from the CCC (40 MHz)
  • many HDMI connectors with configurable transmission (software can control which port will be enabled for both data in and out)
  • all fast commands are sent simultaneously  to all enabled ports
  • DIF packets are merged in the FPGA firmware (~100 byte chunks are merged to up to 2.5 kB)
  • 12-bit bray decoding for data and bxid fields of the SPIROC data packet (
  • TCP/IP server for data communication (both directions)
  • ssh server to log in to the embedded linux and perform debugging

HDMI cable pinout

  • pair 1-3: clk (LDA → DIF)
  • pair 4-6: commands (LDA → DIF)
  • pair 7-9: busy (DIF → LDA)
  • pair 10-12: data (DIF → LDA)
  • pair 15-16: trigger (LDA → DIF)


The LDA handles following proprietary packets:

  • "outgoing" packets (from PC to LDA):
    • Fast commands (from CCC or PC) are broadcasted to all enabled ports
    • System configuration packets configure internal registers of the LDA
    • Standard commands (slow commands): are send to either a specific HDMI port, or to all enabled ports
  • "incoming" packets (from DIF)
    • Standard communication packets
    • Data readout packets
    • LDA system configuration responses
    • LDA timestamps

Outgoing packets (TCP → DIF):

byte #:0123456789101112131415...1617

All outgoing packets need additional header, which adds a Length field

Serial protocol

The communication protocol is a UART-like, 1 start bit, 16 data bits, no parity and 2 stop bits. Example of transmitting a fast command 0xE311:

Supported fast commands (those are issued from CCC):

  • 0xE311 - start of acquisition
  • 0xE313 - stop of acquisition
  • 0xE000 - synchronization fast command (DIF synchronizes its internal 5MHz divided clock to the arrival of this command)
  • 0x0000 - command to reset the LVDS buffer (not needed anymore).



The FPGA has a timestamping core, which has following functionality:

  • Counting of Readout cycles
  • Counting of triggers
  • Timestamp of trigger
  • Timestamp of start + stop of acquisition
  • Timestamp of rising and falling edge of busy (in wing-LDA: only for 1st FPGA)

Timestamps have 25 ns resolution (derived from 40 MHz) and have 48 bits of resolution (will overflow in 81 days)

If there is noise on the trigger input and timestamping is enabled, the LDA becomes flooded by the timestamp packets and communication is problematic. If this happens, just disable the timestamping and flush the LDA buffers.

TCP communication

low-level access

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