As a result of a conversation with SLAC, it was said that the clock periods set in KPiX all switch depending on the state the KPiX is in. Therefore it could be that some clock lines do not switch at the correct time and could therefore result in the asynchronicity.
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06.08.2018, Sensor 52 KpiX 1
One LVDS probe was connected to the LVDS clock of KPiX 1 on sensor 52. In addition, the AVDD power line was probed to be able to discern the part of the KPiX cycle we are in and to trigger the system.
- Overall clock and AVDD cycle for KPiX. The weird reduction of the current during the acquisition period was found in multiple triggers
The clock shows the switch from digitization to readout, clock changed to ClkPeriodRead ~ 50us before the End Of Digi pulse
These pictures show the clock during digitization. The first two pictures show the fourth precharge clock period during digitization in two different zoom factors.
- The pictures show the change from the startup idle clock to the acq. clock. The pictures are simply there for the measurement of the two clocks
- At the start of the data acquisition, a short part with a longer single clock period was found. It showed a length of 135 ns
06.08.2018, Sensor 52 BOTH KPiX
One LVDS probe was connected to the LVDS clock of both KPiX on sensor 52. In addition, the AVDD power line was probed to be able to discern the part of the KPiX cycle we are in and to trigger the system.
In addition the raw data was recorded for analysis.
End of DIGI + Start Of Read
The pictures show the clock and power at the end of digitization with the start of data readout. The data taking is asynchronous as can be seen by the two peaks in the power draw. On the other hand, the clocks change at the exact same point in time.
ClkPeriodPrecharge + ClkPeriodDig
First pictures shows the precharge clock, and the second picture shows the beginning of digitization clock right after precharge.
Picture below shows the end of data acquisition clock: