Page tree

Versions Compared


  • This line was added.
  • This line was removed.
  • Formatting was changed.


RBCP AddressModeResetReigister
0x00000000W0x00Command Register
0x10000001RW0x00ALPIDE ChipID under Test
0x10000002RW0x00ALPIDE Register Address to Read or Write[15:8]
0x10000003RW0x00ALPIDE Register Address to Read or Write[7:0]
0x10000004RW0x00Data Wrote to ALPIDE Register [15:8]
0x10000005RW0x00Data Wrote to ALPIDE Register [7:0]
0x10000006RW0x00Broadcast OPCODE
0x10000007RW0x00Trigger Delay in Step of 25 ns[15:8]
0x10000008RW0x00Trigger Delay in Step of 25 ns[7:0]
0x10000009RW0x00Reserved. Not used now.
0x1000000aRW0x00Reserved. Not used now.
0x1000000bRW0x00Gap of Internal Trigger in Step of 5μs[15:8]
0x1000000cRW0x14Gap of Internal Trigger in Step of 5μs[7:0]
0x1000000dR0x00Succeed Read Counts
0x1000000eR0x00Data Read from ALPIDE Register[15:8]

Data Read from ALPIDE Register[7:0]

0x10000010RW0x00FPGA Working Mode
0xFFFFFC18RW0xc0SiTCP IP_addrres 3address_base[31:24]
0xFFFFFC19RW0xa8SiTCP IP_addrres 2address_base[23:16]
0xFFFFFC1aRW0x0aSiTCP IP_addrres 1address_base[15:8]
0xFFFFFC1bRW0x10SiTCP IP_addrres 0address_base[7:0]
SiTCP IP EEPROM  write enable renew (write Zero to it, and then write IP_address word_base)

0x00000000 Command Register
The command register is a special register allowing the execution of internal operations or sequences. The valid command codes are list as below.
0xFF: Reset the DAQ System including all the registers. The SiTCP would need 3-4 seconds to reconnect.
0x50: Broadcast command in the Broadcast OPCODE register to ALPIDE chip.
0x9C: Write data in Data Wrote to ALPIDE register at ALPIDE Register Address.
0x4E: Read data from ALPIDE register at ALPIDE Register Address and store in Data Read.


0x10000010 FPGA Mode
This register controls the working mode of the DAQ system.
Bit 7:2 - Not used.
Bit 1 - 1: Internal trigger mode. 0: External trigger mode.
Bit 0 - 1: ALPIDE samples frame data continuously. 0: ALPIDE IDLE.

0xFFFFFC18-B  EEPROM IP address base

The base IP address is stored in EEPROM.  The run-time ip address[7:8] is  the sum of  value in 0xFFFFFC  and onboard switch state.

0xFFFFFCFF   EEPROM IP address write enable.

Only after a Zero  is written to this,  the EEPROM IP address will be writable.