|0x10000001||RW||0x00||ALPIDE ChipID under Test|
|0x10000002||RW||0x00||ALPIDE Register Address to Read or Write[15:8]|
|0x10000003||RW||0x00||ALPIDE Register Address to Read or Write[7:0]|
|0x10000004||RW||0x00||Data Wrote to ALPIDE Register [15:8]|
|0x10000005||RW||0x00||Data Wrote to ALPIDE Register [7:0]|
|0x10000007||RW||0x00||Trigger Delay in Step of 25 ns[15:8]|
|0x10000008||RW||0x00||Trigger Delay in Step of 25 ns[7:0]|
|0x10000009||RW||0x00||Reserved. Not used now.|
|0x1000000a||RW||0x00||Reserved. Not used now.|
|0x1000000b||RW||0x00||Gap of Internal Trigger in Step of 5μs[15:8]|
|0x1000000c||RW||0x14||Gap of Internal Trigger in Step of 5μs[7:0]|
|0x1000000d||R||0x00||Succeed Read Counts|
|0x1000000e||R||0x00||Data Read from ALPIDE Register[15:8]|
Data Read from ALPIDE Register[7:0]
|0x10000010||RW||0x00||FPGA Working Mode|
|0xFFFFFC18||RW||0xc0||SiTCP IP_addrres 3address_base[31:24]|
|0xFFFFFC19||RW||0xa8||SiTCP IP_addrres 2address_base[23:16]|
|0xFFFFFC1a||RW||0x0a||SiTCP IP_addrres 1address_base[15:8]|
|0xFFFFFC1b||RW||0x10||SiTCP IP_addrres 0address_base[7:0]|
|0xFFFFFCFF||W||SiTCP IP EEPROM write enable renew (write Zero to it, and then write IP_address word_base)|
0x00000000 Command Register
The command register is a special register allowing the execution of internal operations or sequences. The valid command codes are list as below.
0xFF: Reset the DAQ System including all the registers. The SiTCP would need 3-4 seconds to reconnect.
0x50: Broadcast command in the Broadcast OPCODE register to ALPIDE chip.
0x9C: Write data in Data Wrote to ALPIDE register at ALPIDE Register Address.
0x4E: Read data from ALPIDE register at ALPIDE Register Address and store in Data Read.
0x10000010 FPGA Mode
This register controls the working mode of the DAQ system.
Bit 7:2 - Not used.
Bit 1 - 1: Internal trigger mode. 0: External trigger mode.
Bit 0 - 1: ALPIDE samples frame data continuously. 0: ALPIDE IDLE.
0xFFFFFC18-B EEPROM IP address base
The base IP address is stored in EEPROM. The run-time ip address[7:8] is the sum of value in 0xFFFFFC and onboard switch state.
0xFFFFFCFF EEPROM IP address write enable.
Only after a Zero is written to this, the EEPROM IP address will be writable.