- Firmware: TLU_v1E, 22.10.2017 (incl. ignore BUSY option for EUDET mode):
- Manual: In the repo above
- Hardware descriptions: on OHW
Install drivers for Digilent JTAG HS-2
service udev restart
Power and connect USB to PC
lsusb: Bus 001 Device 004: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
Flash bitfile and memory file
following these instructions: https://webapps-pp.bris.ac.uk/elog/AIDA/68
In a nutshell:
install the Xilinx tools on a PC (e.g. in Lab4): https://www.xilinx.com/support/download.html
connect a USB cable on the back of the TLU to the PC
Upload Bitfile: https://github.com/PaoloGB/firmware_AIDA/blob/master/bitFiles/top_tlu_v1e_0x1e00000a.bit
Upload memory configuration file, used to autoconfigure the firmware on power-up: https://github.com/PaoloGB/firmware_AIDA/blob/master/bitFiles/v1e_memoryConf_0x1e00000a.mcs
Starting the TLU
IP address of TLU: 192.168.200.30
- Setup local network 192.168.200.xxx
- Settings to remember
- If you power cycle the TLU you need to re-configure the clock by setting CONFCLOCK=1 in the INI file.
- Disable std print out: DISABLE_PRINT = 1
- Python Scripts
in the attached picture I show what you should see inside the box.
The FPGA will be different but what you actually want to see is the PCB.
The connector J1 is shown in the red circle and should be easy to find and to probe.
As mentioned, it should have
3.3 V on pin 1 and 2
GND on pin 3
5 V on pin 15
-5V on pin 16
Pin 12 is the DATA for the I2C line
Pin 14 is the CLOCK for the I2C line
If you check any of those with a scope, you should see activity whenever you press the INIT button,
because the FPGA will try to talk to the I2C slaves on the PCB.
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