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1.1Now 2020First Release

General:

The Fast shutter Controller is a Firmware for the PiLC to generate gate signals that is

synchronized with an external signal.

The gate signal can defined as follow:

NameTaskValue
ControlControlling the gate

0= Reset

1= Arm

2= Gate manually open

Gate DelayDelay from the rising edge from the external signal and the rising edge from the gateTime in us (32bit)
Gate HighHigh Time from the gateTime in us (32bit)
Gate LowLow Time from the gateTime in us (32bit)
Gate RepletionHow often the gate should be repeat

Instruction:

Before you Arm the system the Gate Delay/High/Low and Repletion must be set. This setting must only set once.

Example: Make a Gate 2sec after the external rising edge, 2sec  High Time, 2sec  Low Time and repeat it 5 times.

Pyhton:

pilc.WriteFPGA([0x03,2000000]) #Delay

pilc.WriteFPGA([0x05,2000000]) # High time

pilc.WriteFPGA([0x07,2000000]) # Low Time

pilc.WriteFPGA([0x09,5]) # Repeat


After the gate defines a set. It is possible to set now the control to arm.

Pyhton:

pilc.WriteFPGA([0x01,1]) # Cntrl


When the Gates are produce and you want to start a new run you must reset the control

Pyhton:

pilc.WriteFPGA([0x01,0]) # Cntrl

Also you can stop the gate, when you reset the control.

PiLC I/Os:


NumberTypFunction
1InputTrigger
2OutputGate/Shutter
3OutputBusy
4N/AN/A
5N/AN/A
6N/AN/A
7N/AN/A
8N/AN/A
9N/AN/A
10N/AN/A
11N/AN/A
12N/AN/A
13N/AN/A
14N/AN/A
15N/AN/A
16N/AN/A


PiLC Register:

NumberIn RegisterOut Register
1ControlRemain Gates
2Gate Delay in usN/A
3Gate High Time in usN/A
4Gate Low Time in usN/A
5Gate QuantityN/A
6N/AN/A
7N/AN/A
8N/AN/A
9N/AN/A
10N/AN/A
11N/AN/A
12N/AN/A
13N/AN/A
14N/AN/A
15N/AN/A
16N/AN/A
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