Fast command packets

Supported fast commands from CCC:

  • 0xE311 - start of acquisition
  • 0xE313 - stop of acquisition
  • 0xE000 - synchronization fast command (DIF synchronizes its internal 5MHz divided clock to the arrival of this command)
  • 0x0000 - command to reset the LVDS buffer (not needed anymore).


hex UART code

8b10b code


start acquisition


K28.3 + D2.1

start of acquisition

stop acquisition


K28.3 + D2.3

stop of acquisition



K28.0 + D0.0

Synchronize phases of 5 MHz derived clocks among layers

recover reciever0x0000--debug only, not needed anymore
flow stop0xE519K28.5 + D3.1"I am full, don't send me any data". Valid for 1 ms
flow continue0xE51AK28.5 + D3.1"I am ready to receive data"

Thise commands are transmitted serially. The communication protocol is a UART-like, 1 start bit, 16 data bits, no parity and 2 stop bits. Example of transmitting a fast command 0xE311:

Fast commands can be send from the mini-LDA directly (not wing-LDA). LDA accepts following format (Start acquisition example):

byte #:012345

bytes #0-3 are fixed length (2 byte), bytes 5 and 4 are the fast command. Additional zeroes (as byte 6 and 7) are needed when sending directly to the character node in petalinux.

LDA TCP packets (PC → LDA → DIF)

The LDA accepts DIF standard packets in following format:

byte #:0123456789101112131415...1617

Length: the length of the following packet (length field itself doesn't count). Little endian (LSB is on byte index 0)

type: should be 02

port: address where will be the packet sent



0x00 - 0x5F

DIF standard command to be sent to a specific port number from the range of 0x00 to 0x5F (ports 0 to 95). This value is changed to 0xCC when sending to DIF.

0x60 - 0x7F



read from a LDA register

0x81 - 0x82

reserved for setting and clearing bits from the LDA register


Write to the LDA register


broadcast to all ports (address is changed to 0xCC02 when it is sent to DIF)

LDA address space

LDA registers can be addressed using a dedicated port2 values: 0x80 (read from the register) and 0x83 (write to the register). The format is same for both and write. LDA responses to this command.

byte #:01234567891011


  • Length: fixed to 0x08 for these packets
  • type: must be 2
  • port: 0x80 = read from the address, 0x83 = write to the address
  • addr: address to the configuration register
  • dest: either a port number (0..95), or FPGA system ports (0x80, 0x81, 0x90)

Port configuration address space:

byte #:01234567891011
data0x080000x020x80-0x83addr0x00-0x5F (the port #)data_Ldata_H0xABAB

Address registers:

addr 0x0000  (index 0) port enable 
              bit 0: CONFIG_PORT_ENABLED
addr 0x0002  (index 1) configuration
              bits 2..0: CONFIG_RX_TIMEOUT0
              bits 6..4: CONFIG_RX_TIMEOUT1
              bit 8    : CONFIG_RX_MERGE_ROP               
addr 0x0004  (index 2) status
              bit  0     : STATUS_RX_IDLE                
              bit  1     : STATUS_RX_CRC_OK                         
              bits 10..8 : STATUS_RX_FSMSTATUS           
addr 0x0006  (index 3) status
              bit  0    : ERROR_RX_PACKET_FORMAT ;                
              bit  1    : ERROR_RX_PACKETID;                  
              bit  2    : ERROR_RX_PACKET_ORDER;              
              bit  3    : ERROR_RX_CHAINSOURCE_MISMATCH;      
              bit  4    : ERROR_RX_TIMEOUT0;                  
              bit  5    : ERROR_RX_TIMEOUT1;                  
              bit  6    : ERROR_RX_LENGTH_OVERFLOW;           
              bit  7    : ERROR_RX_CRC;                       
              bit  8    : ERROR_RX_INVALID_STATE;             
              bit  9    ; ERROR_RX_POINTER_OVERWRITTEN;       
addr 0x0008 (index 4) idelay  (TODO)
addr 0x000A (index 5) odelay  (TODO)
addr 0x000C (index 6) 
addr 0x000E (index 7) 

Mini-LDA system configuration address space:

byte #:01234567891011

Address registers:

addr 0x00 (index0) config
    bit 0: busy extend 1 - extend the busy until the packet Queue is read out (last packet might be still in progress)
    bit 1: busy extend 2 - extent the busy until the DMA fifo get empty. Not implemented
    bit 2: timestamping packets are sent
    bit 15: initiate a reset. no reply on this message
addr 0x02 (index 1)
    bits 9..0 busy signals of the 
addr 0x04 (index 2) -- reserved for wing-lda
addr 0x06 (index 3) -- Readout  cycle
addr 0x08 (index 4) -- Trigger ID

Wing-LDA system kintex address space:

byte #:01234567891011

byte #7 is a kintex designator (x80=kintex1, x81=kintex2, ...)


addr 0x00 (index0) config
    bit 0: busy extend 1 - extend the busy until the packet Queue is read out (last packet might be still in progress)
    bit 1: busy extend 2 - extent the busy until the DMA fifo get empty. Not implemented
    bit 2: timestamping packets are sent
    bit 15: initiate a reset. no reply on this message
addr 0x02 (index 1) -- busy signals
    bits 15..0 busy signals of the ports 0-15
addr 0x04 (index 2) --busy signals
    bits 7..0  busy signals of the ports 23..16
addr 0x06 (index 3) -- Readout  cycle
addr 0x08 (index 4) -- Trigger ID
addr 0x0A (index 5) -- set/get HSlink idelay calibration
    ??? TODO finish the documentation
    value 0x8001 : start calibration
    value 0x31nn : set the idelay to nn (lowest 5 bits)
    on read: results of the calibration indexed bits(7-5)(4-0), result is 10 bits
    ??? bit 4-0 : delay to store (or which delay sample to read)
    ??? bit 7-3 : port (currently 2 HS link ports, so 000 or 001)
    ??? bit 15: start the internal calibration and take samples (other bits bust be 0)

Wing-LDA system Mars address space:

byte #:01234567891011
addr 0x00 (index0) config
    bit 0: Kintex 1 enable
    bit 1: Kintex 2 enable
    bit 2: Kintex 3 enable
    bit 3: Kintex 4 enable
    bit 4: Packet generation enable
    bit 15: initiate a reset. no reply on this message
addr 0x02 (index 1)
    bits 3..0: busy signals of the kintexes

 addr 0x10-0x1E: traffic generation 
addr 0x10 (index 8)
   bits 7 downto 0: number of layers connected
addr 0x12 (index 9)
   bits 3 downto 0: maximum length of the packet. 0 = 1 trigger,  15 = 16 triggers
   bit 8: random length (not implemented)
addr 0x14 (index 10)
   bits 2 downto 0: number of readout chains. 0 = 1 readout chain, 3 = 4readout chains
   bits 11 downto 8: number of chips in the readout chain. 0=1chip, 3=4chips
addr 0x16 (index 11)
   bits 3 downto 0: wait time between readout cycles. How many ms will wait logaritmic: 2^cycle_delays. 0 = 0-1ms delay, 2=3-4ms delay

 addr 0x20 - 0x2E: 
addr 0x20 (index 16): control of the delay adjustment

LDA TCP packets (LDA → PC)


All packets from LDA have a following 8-byte header:

byte #:01234567
dataLength(Lo)Length(Hi)ReadOutCycle0LDA#Port#status (Lo)Status (Hi)

The 16-bit length indicates the length of the remaining data. It should be <4k and should be an even number.

  • Status(Lo):
    • bit 0 (0x01): RX packet format error
    • bit 1 (0x02): RX packetID error
    • bit 2 (0x04): RX packet order error
    • bit 3 (0x08): RX readout chain and chip number source mismatch error
    • bit 4 (0x10): RX timeout0 error
    • bit 5 (0x20): RX timeout2 error
    • bit 6 (0x40): RX length overflow error
    • bit 7 (0x80): RX CRC error
  • Shatus(Hi)
    • bit 0 (0x01): (reserved)
    • bit 1 (0x02): (reserved)
    • bit 2 (0x04): (reserved)
    • bit 3 (0x08): Timestamp packets
    • bit 4 (0x10): Config packets
    • bit 5 (0x20): Merged packet
    • bit 6 (0x40): ASIC readout packet subtype
    • bit 7 (0x80): Readout packet type

Timestamping packets

byte #:0-7891011121314-1516-2122-23
dataHeader0x450x4D0x490x54TS_type00ROC/trig#TS (48-bit)0xABAB

Header → status is 0x0800

Header → port# is usually 0xA0


  • 0x01: acq start
  • 0x02: acq stop
  • 0x03: sync packet
  • 0x10: new trigger
  • 0x11: new ROC (caused by acq_stop)
  • 0x20: busy falling edge (HBUs ready to start)
  • 0x21: busy rising edge (HBUs raise busy)

ROC/trig# is a shared field, which shows the readout cycle except for the trigger event, where a trigger number is stored instead.

The readout cycles for the packets are adjusted in the LDA so that followin sequence has a same ROC: acq_start, (triggers), busy_rising, acq_stop, new_ROC, busy_falling. If the new_ROC and ACQ_STOP comes before the busy_risin, the busy_risin will have an incorrect ROC (+1)

Note: some earlier version of LDA had reversed TS types for busy raising and falling

ASIC Readout packets

byte #:0-7891011121314-1516...len+5len+6,len+7

Wing-LDA 8b10b code extension

The wing-LDA is internally using the FPGA ↔ FPGA link, which uses 8b10b natively, using following commands. 2 words are transmitted in parallelAdditional to this, Wing-LDA is internally using 

SEQ_IDLEK28.1 + K28.1nothing to transmit
SEQ_IDLE_FULLK28.5 + D5.6buffer is full, nothing to transmit
SEQ_FSTARTK27.7 + K23.7Frame start (start of the packet)
SEQ_FENDK29.7 + K23.7Frame end (end of the packet)
SEQ_ACKK28.5 + D21.0 Acknowledge answer. Packet was successfuly received
SEQ_NACKK28.5 + D21.3Not acknowledged - error with packet CRC, please resend
SEQ_STOPK28.5 + D3.1Buffer just got full
SEQ_CONTK28.5 + D3.2Buffer is empty again, continue

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