Mezzanine revisions

There exist two revisions of the mezzanine:

  • V2: "older" revision from 2014. 
  • V0: "new" revision from 2018, which has an older footprint. Those mezzanines were hand repaired and fully working

revisions need different firmware

Both revisions are side by side on following picture (click for zoom). Key differences

  • text above the FMC connector (V0)
  • QR code (V0)
  • different discrete component R13 in the middle of the board(V2)
  • hand soldering on the board (V0)

Port assignment

The internal architecture:

Receiving path:

Packets from DIF are built in dif_port → rx_manager module. The ASIC packet from DIF has in principle 2.5 kB, but the DIF sends those packets cut into 100bytes. Those small packets are merged into a single packet in the BRAM and information about the packet is sent to a rx_queue. Packets are stored to the BRAM in a circular way, so the new packet is overwriting the old ones. The rx_queue concentrates information about all packets from all ports: the length of the packets, where in the BRAM the packet actually is and other information. The dif_port has typically a memory for  few big packets (corresponds to ~1.7 HBU). The queue has a size of 512 packet headers.

mem_man_axis → mem_man_axis_rx is collecting the packets from the BRAMS of all HDMI ports (dif_ports), adds a header (Packets#Header), trims to the proper length on the AXI4-Stream bus (using tkeeb signal) and sends the packet out. The end of the packet is marked with tlast=1. The memory manager has a large fifo: ~256 kB.

Timestamping module stores timestamp of internal events. can store ~2.5k timestamps. The  FIFO output directly is AXI4-Stream

Streams of timestamps and DIF packetsare merged via standard  AXI4-Stream interconnect, with an arbitration priority given to the timestamps packets. 

axi_merge_fifo sends the data directly to the DMA IP (not shown on picture). THe performance of DMA is much higher, when it treats larger packets instead of small packets

LED debug signals

The Zedboard has 8 internal LEDs, that are used to debug the AXI bus for the AXI-DMA core. The meaning of the LEDs are following:

LEDVHDL signal nameMeaning
0TX_AXIS_MM2S_tvalidThere is data available from the processor
1TX_AXIS_MM2S_tready_intThe FPGA is ready to receive data
2RX_AXIS_S2MM_treadyThe processor (the AXI-DMA core) is ready to receive the data
3RX_AXIS_S2MM_tvalid_intThere is data available from the FPGA
4CCC_HDMI_BUSY_intbusy signal sent to the CCC (a sum of HBU modules and data transfer readiness)
5-(not used)
6-(not used)
7-(not used)

Internal packet generator

packet generator is controlled by the buttons and switches. Buttons are used to latch values given by switches. 

Description: Controls the packet generation via buttons and switches.
  BTN UP: switch on
     SW7-0: number of layers
  BTN DOWN: switches off generation
  BTN Left:
       |  SW7..SW4     | SW3..SW0       |
       | # of chains   | asics in chain |
  BTN right:
       |  SW7..SW4     | SW3..SW0       |
       |   delay       | memcells       |

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