- Mainz megatile. HBU 5, module 43
- mini-LDA V0 (svn rev.508, trunk: firmware https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/xlda/trunk/)
- stadalone for first test: svn rev 508 https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/ccc/trunk/
- with telescope: https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/ccc/branches/Slave_of_EUDET-TLU/
- 10 x 10 cm scintillators connected to the nim logic and connected to the BIF input PX2 (input 3)
Counter A (Vertical): +1450 V
Counter B (Horizontal): +1500 V
- Trigger input 0 used up to run 64894
- Trigger input 3 (the default) used from run 64895 onwards
TDC investigation (Spiroc 2e feature)
THe SPIROC 2e has a know problem, that the TDC value jumps by 27~33 ns depending on the stopping condition.
New firmware with a different acquisition timing and different condition to stop is at retiming branch in the desy svn. (TODO link)
Quick test of problem existence
I picked a run # 66390 - run with absorber, >300000 evts, hitting mostly channel 8.
Quick plotting in gnuplot:
(click to ziim the pictures)
bad for memory cells 0..14 (they can be stopped externally):
The only OK memory cell is 15, because that fills the ASIC and then it stops by itself:
New DIF firmware:
BIF: 19019 (yes, much different!)
It seems, that the hypothesis on stopping BXID parity was correct. Red: run 66394 (even bxid), blue:66393 (odd bxid):
ILC mode with new firmware
stopping at even bxid
LDA offset 285
BIF offset 9290
Run data quality check
BIF statistics summary
It seems, that something went wrong with the BIF - it was slipping a clock cycle quite often.
Some clock phase changes are to be expected (restarting the CCC), some are unexpected.
Run number vs. timestamp (color is the start_acquisition phase):
Bif offsets varying a bit (position?): 67397. (67381~67405)