The CCC works as a slave (dependent) device to the CMS HGCAL sync board. The pinout on the CCC differs in 2 aspects:
- User port of the CCC needs to be connected through the pin-swapping HDMI-to-HDMI adapter to the HGCAL sync board.
- Veto output replaces the clock output in the standard configuration. It is used only when it the user port is enabled ("evaluate_user")
The CCC can run standalone without HGCAL, but it was not designed to dynamically switch clocks between HGCAL and its own. Restart is needed after change of clock source
If the clock source from HGCAL stops, the AHCAL DAQ will crash. Restart is needed after the clock will become stable
"User" HDMI Pinout and signal description
- CLK40 (pair 1-3): clock input
- TRIG (pair 4-6): trigger from Sync board. LVDS signal from SYNC board to readout board indicating that there has been an event that needs to be recorded. Use a D-flip-flop on rising edge of 40 MHz clock. Trigger pulse will be high for many ticks (roughly 40). Create your own pulse width. (The TRIG pulse is low latency, and untouched by firmware.)
- WAITING_FOR_TRIG (pair 7-9): LVDS signal from SYNC to all of the readout boards indicating that the system should be recording data while waiting for a trigger pulse. This signal will go low during a trigger pulse and remain low until all of the readout boards have gathered and recorded all of the data associated with the trigger pulse.
- READOUT_DONE (pair 10-12) LVDS signal from SYNC to all of the readout boards indicating that the system should be recording data while waiting for a trigger pulse. This signal will go low during a trigger pulse and remain low until all of the readout boards have gathered and recorded all of the data associated with the trigger pulse.
- CLEARB (pair 15-16): LVDS signal from SYNC board to readout board, low speed. Active low. When this signal is low, the system should completely reinitialize and prepare for a new run.
The time diagram (wavedrom link) shows 2 AHCAL acquisition cycles in the combined mode with CMS HGCAL. A trigger is received in the first case. In the second cycle no trigger arrives and AHCAL stops on timeout.
Following signals are conditioned:
In order to filter possible glitches, a parametric hardware glitch filter is used with configuration of minwidth_*=1 and keep_*=4:
following glitch filterinprevent glitches to change the
Debugging LEDs and signals
based on switch configuration SW7..SW0 (mind the bit order
|LD0||acquisition||trig_id(0) - LSB||trig_id(8)|
|LD5||alive_counter (should blink)||trig_id(5);||trig_id(13)|
|LD6||gclk_locked (clock locked)||trig_id(6);||trig_id(14)|
|LD7||hgcal_clk40_locked (HGCAL clock in use)||trig_id(7);||trig_id(15) - MSB|
- JA1 <= clock
- JA2 <= HDMI_HGCAL_TRIG
- JA3 <= HDMI_HGCAL_WAITING
- JA4 <= HDMI_HGCAL_RDDONE
- JB1 <= busy
- JB2 <= acquisition
- JB3 <= '0';
- JB4 <= CONTROL_T (fast commands UART)
Xml tags, that control the behavior for combined running:
- stop_on_hgcal_waiting_fall: whether to stop upon the sync board trigger arrival (WAITING_FOR_TRIGGER goes low)
- start_on_hgcal_waiting_rise: whether to restart AHCAL acquisition with the rising edge of the WAITING_FOR_TRIGGER signal
- evaluate_user: The user port must be enabled if the veto signal is to be send to HGCAL sync. When disabled, AHCAL can run independently and AHCAL running will not disturb the HGCAL
- veto_delay_pp: whether to use larger delay of 14300 clock tics (when powerpulsing is enabled) or 2300 clock tics (when powerpulsing is disabled
Compilation and binaries
The location of the source files as well as binaries is https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/ccc/branches/CMS_HGCAL/ . Compilation procedure is similar to the trunk version