The CCC works as a slave (dependent) device to the CMS HGCAL sync board. The pinout on the CCC differs in 2 aspects:
- User port of the CCC needs to be connected through the pin-swapping HDMI-to-HDMI adapter to the HGCAL sync board.
- Veto output replaces the clock output in the standard configuration. It is used only when it the user port is enabled ("evaluate_user")
"User" HDMI Pinout and signal description
- CLK40 (pair 1-3): clock input
- TRIG (pair 4-6): trigger from Sync board. LVDS signal from SYNC board to readout board indicating that there has been an event that needs to be recorded. Use a D-flip-flop on rising edge of 40 MHz clock. Trigger pulse will be high for many ticks (roughly 40). Create your own pulse width. (The TRIG pulse is low latency, and untouched by firmware.)
- WAITING_FOR_TRIG (pair 7-9): LVDS signal from SYNC to all of the readout boards indicating that the system should be recording data while waiting for a trigger pulse. This signal will go low during a trigger pulse and remain low until all of the readout boards have gathered and recorded all of the data associated with the trigger pulse.
- READOUT_DONE (pair 10-12) LVDS signal from SYNC to all of the readout boards indicating that the system should be recording data while waiting for a trigger pulse. This signal will go low during a trigger pulse and remain low until all of the readout boards have gathered and recorded all of the data associated with the trigger pulse.
- CLEARB (pair 15-16): LVDS signal from SYNC board to readout board, low speed. Active low. When this signal is low, the system should completely reinitialize and prepare for a new run.
The time diagram (wavedrom link) shows 2 AHCAL acquisition cycles in the combined mode with CMS HGCAL. A trigger is received in the first case. In the second cycle no trigger arrives and AHCAL stops on timeout.
wavedrom_source.json
Signal filtering
Following signals are conditioned:
- WAITING_FOR_TRIG
- TRIGGER
- CLEARB
In order to filter possible glitches, a parametric hardware glitch filter is used with configuration of minwidth_*=1 and keep_*=4:
-- Parameters:
-- minwidth_positive - minimum positive pulse width. 1=no filtering. Delays the signal!
-- minwidth_negative - minimum negative pulse width. 1=no filtering. Delays the signal!
-- keep_positive - how many clock cycles to keep '1' on the output after the rising edge.
-- 1=no filtering
-- in case of combining with minwidth_positive, minwidth_positive
-- filter is applied first
-- keep_negative - how many clock cycles to keep '1' on the output after the falling edge.
-- Minimal pulse width filtering:
-- length: 1cc 2cc 3cc 4cc 5cc
-- _ __ ___ ____
-- in: _/\_____/ \_____/ \_____/ \_____/ \____
-- 0100000011000000111000000111100000011111000000
-- _ __ ___ ____
-- min=1: _/\_____/ \_____/ \_____/ \_____/ \____
-- 0100000011000000111000000111100000011111000000
-- (basically no filtering)
-- _ __ ___ ____
-- min=2: _________/ \_____/ \_____/ \_____/ \___
-- 000000000110000001110000001111000000111110000
-- __ ___ ____
-- min=3: __________________/ \_____/ \_____/ \__
-- 000000000000000000111000000111100000011111000
--
-- glitches after the rising edge
-- ___ ___ _ ___ _ ___
-- input: _/\/ \___/\_/ \____/ \/ \____/ \_/ \____
-- 010111100001001111000001101111000001100111100000
-- ___ ___ _ ___ _ ___
-- out1: _/\/ \___/\_/ \____/ \/ \____/ \_/ \____
-- 010111100001001111000001101111000001100111100000
-- (minwidth=1,keep1=2, keep0=2)
-- _____ _ __ _ __ _ ___
-- out2: _/ \___/ \_/ \____/ \_/ \____/ \_/ \____
-- 011111100001100111100001100111000001100111100000
-- (minwidth=1,keep1=2, keep0=2)
-- _____ ______ ______ __ __
-- out3: _/ \___/ \____/ \____/ \__/ \___
-- 011111100001111111000001111111000001110001110000
-- (minwidth=1,keep1=3, keep0=3)
-- _____ ______ ______ _______
-- out4: _/ \___/ \____/ \____/ \____
-- 011111100001111111000001111111000001111111100000
-- (minwidth=1,keep1=4, keep0=4)
--
-- When both minwidth and keeps are defined, signal is filtered
-- first for the minimum pulse width. Afterward, minimum output
-- pulse length filtering is applied. Example:
-- ___ ___ _ ___ _ ___
-- input: _/\/ \___/\_/ \____/ \/ \____/ \_/ \____
-- input: 010111100001001111000001101111000001100111100000
-- minwidth: 000011110000000111100000111111100000110011110000 (step1)
-- ___ ___ ______ _ ___
-- out2-2: ____/ \______/ \____/ \____/ \_/ \___
-- 000011110000000111100000111111100000110011110000 (step2)
-- (minwidth=2,keep1=2, keep0=2)
-- ___ ___ ______ __ __
-- out3-2: ____/ \______/ \____/ \____/ \__/ \__
-- 000011110000000111100000111111100000111000111000 (step2)
-- (minwidth=2,keep1=3, keep0=3)
-- ___ ___ ______ _______
-- out4-2: ____/ \______/ \____/ \____/ \__
-- 000011110000000111100000111111100000111111110000 (step2)
-- (minwidth=2,keep1=4, keep0=4)
following glitch filterinprevent glitches to change the
Debugging LEDs and signals
detailed description
LEDS
based on switch configuration SW7..SW0 (mind the bit order
| LED | SW=00000000 | SW=00000001 | SW=00000010 |
|---|
| LD0 | acquisition | trig_id(0) - LSB | trig_id(8) |
| LD1 | busy | trig_id(1); | trig_id(9) |
| LD2 | HDMI_HGCAL_TRIG | trig_id(2); | trig_id(10) |
| LD3 | HDMI_HGCAL_WAITING | trig_id(3); | trig_id(11) |
| LD4 | HDMI_HGCAL_RDDONE | trig_id(4); | trig_id(12) |
| LD5 | alive_counter (should blink) | trig_id(5); | trig_id(13) |
| LD6 | gclk_locked (clock locked) | trig_id(6); | trig_id(14) |
| LD7 | hgcal_clk40_locked (HGCAL clock in use) | trig_id(7); | trig_id(15) - MSB |
- JA1 <= clock
- JA2 <= HDMI_HGCAL_TRIG
- JA3 <= HDMI_HGCAL_WAITING
- JA4 <= HDMI_HGCAL_RDDONE
- JB1 <= busy
- JB2 <= acquisition
- JB3 <= '0';
- JB4 <= CONTROL_T (fast commands UART)
Configuration
Xml tags, that control the behavior for combined running:
<conf>
<acquisition_mask>
<stop_on_hgcal_waiting_fall>0</stop_on_hgcal_waiting_fall>
<start_on_hgcal_waiting_rise>0</start_on_hgcal_waiting_rise>
</acquisition_mask>
<peripherals_mask>
<evaluate_user>1</evaluate_user>
</peripherals_mask>
<veto_delay_pp>1</veto_delay_pp>
</conf>
- stop_on_hgcal_waiting_fall: whether to stop upon the sync board trigger arrival (WAITING_FOR_TRIGGER goes low)
- start_on_hgcal_waiting_rise: whether to restart AHCAL acquisition with the rising edge of the WAITING_FOR_TRIGGER signal
- evaluate_user: The user port must be enabled if the veto signal is to be send to HGCAL sync. When disabled, AHCAL can run independently and AHCAL running will not disturb the HGCAL
- veto_delay_pp: whether to use larger delay of 14300 clock tics (when powerpulsing is enabled) or 2300 clock tics (when powerpulsing is disabled
Compilation and binaries
The location of the source files as well as binaries is https://svnsrv.desy.de/k5websvn/wsvn/General.ScCalo_DAQ/ccc/branches/CMS_HGCAL/ . Compilation procedure is similar to the trunk version