The CALICE Database has two parts:

  1. Geometry database: composed of 4 main tables
    1. Module description
    2. Module Connection
    3. Module Location
    4. Hardware Connection
  2. Calibration constants database: composed of all the calibration constants needed for analysis of data and simulation (for example: Pedestal, gain, MIP constants, etc.)

Geometry database

Example files are in "calice_cddata/ahc2_mapping"

Module description

The module description's role is to give a correspondence between the module channels and the I-J coordinates (as well as the local x-y coordinates). For instance, a 2x2 HBU module has 576 channels, the I,J coordinates go from 1 to 24. 

For previous testbeams with EBU modules, the I,J translation is a bit more complicated due to the geometry of the EBUs: The EBU tiles are 5x45 mm2 and different readout types (with respect to the tile direction) are tested:

  • Vertical EBU with bottom readout: Module type 3
  • Horizontal EBU with baseline readout: Module type 4

  • Vertical EBU with baseline readout: Module type 5

For HBU, two different module type are defined:
  • Module with single HBU: Module type 1
  • Module with 2x2 HBU: Module type 2

At June/July 2018 testbeam, there is also Module 41 (which we call "Tokyo" module) with 6x6 cm2 tiles. The tiles are glued on 4 PCBs just as a 2x2 HBU module. However, due to the bigger tile size, one tile corresponds to 4 electronic channels, of which only one channel is read out. Since the database requires strict 1-to-1 correspondence between electronic channels and I-J coordinates, the module description has to be treated differently compared to a 2x2 HBU module. Module type 6 is therefore defined. 

The presentation of a 2x2 HBU module with its chips and channels. The I-J axes are also shown for the top readout case. Single HBU module is also presented with the red box. The 6x6 cm2 tile layout of Tokyo module is shown in green dash lines, the bold channel numbers indicate the channels which are connected.

The presentation of a 2x2 HBU module with its chips and channels. The I-J axes are also shown for the top readout case. Single HBU module is also presented with the red box. The 6x6 cm2 tile layout of Tokyo module is shown in green dash lines, the bold channel numbers indicate the channels which are connected.

Remark: The ChipID in the module description starts always from 0. For example: in a single HBU module description, the ChipID goes from 0 to 3. 

Module connection

The module connection is used to define the order of the modules in the stack, which means the global K-coordinate. Here a module type is also needed (and defined similarly to what has been done for the CALICE AHCAL physics prototype). The list of module type is the following:

  • Module with single HBU: Module type 0
  • Module with 2x2 HBU: Module type 2
  • Vertical EBU with bottom readout: Module type 4
  • Horizontal EBU with baseline readout: Module type 6

  • Vertical EBU with baseline readout: Module type 8

  • "Tokyo" module: Module type 10

Module location

The module location is used to define the global x,y,z coordinates. Here again, a module type is needed, and here again, the definition is inherited from the CALICE AHCAL physics prototype: 

  • Module with single HBU: Module type 4
  • Module with 2x2 HBU: Module type 6
  • Vertical EBU with bottom readout: Module type 8
  • Horizontal EBU with baseline readout: Module type 10

  • Vertical EBU with baseline readout: Module type 12

  • "Tokyo" module: Module type 14

Hardware connection

Since nowhere in the module description/connection/location a real ChipID is provided, a connection to the real ChipID has to be made (see Remark of the Module description section). This connection is provided in the Hardware connection database. The structure is the following: 

Real_ChipID         ModuleID        ChipID (in Module description)


Write to database

To write to database, run the writeHBUGeometrydata.sh file. Make sure to adapt the time stamps!

It will run the create* files one by one. (https://stash.desy.de/projects/CALICE/repos/calice_cddata/browse/ahc2_mapping/Template)


createEPTDescription.cc requires a ModuleDescription.txt file and the time stamp needs to be changed inside of the file. Examples can be found here: https://stash.desy.de/projects/CALICE/repos/calice_cddata/browse/ahc2_mapping/ModuleDescriptions

createEPTModuleConnection.cc: Adapt time stamp; adapt according to comments

createEPTModuleLocation.cc: Adapt time stamp; adapt according to comments

createHardwareConnection.cc: Adapt time stamp; adapt HardwareConnection.txt


The geometry files are not tagged, the most recent version in "HEAD".

Calibration constants database

Existing constants and how their structure needs to be (July 2021). Default values are states in brackets, just fill the whole collum with it.

pedestal_constants

#Module       Chip       Chn       Mean       Error       status(=1)

pedestalMemoryCellOffset

#Module       Chip       Chn       PedOffset[i]       Error[i]       status[i](=1)

lowGainPedestal

#Module       Chip       Chn       Mean       Error       status

lowGainPedestalMemoryCellOffset

#Module       Chip       Chn       PedOffset[i]       Error[i]       status[i](=1)

gain_constants

#Module       Chip       Chn       Gain       Error       Ref(=0)       Ref_error(=0)

gain_slopes

#Module       Chip       Chn       slope       err(=0)

mip_constants

#Module       Chip       Chn       Mip       MipError       Ref       Ref_error(=0)

mip_slopes

#Module       Chip       Chn       slope       err(=0)

DeadCellMap

#Module       Chip       Chn       status

SaturationParameters

#Module       Chip       Chn       npix(=2553)       fraction(=1)       epsilon(=1)

Intercalibration

#Module       Chip       Chn       IC       Error       Ref(=0)       Ref_err(=0)

PhysicsCalibIntercalibration

#Module       Chip       Chn       ICCalib       Error       Ref(=0)       Ref_err(=0)

TimeOffset

#Module       Chip       Chn       Ped[i]       PedErr[i]       status[i](=1)

TimeSlopes

#Module       Chip       Chn       Slope[i]       SlopeErr[i]       status[i](=1)

TimeOffsets_MemOdd

#Module       Chip       Chn       MemOffsetOdd[i]       MemOffsetOddErr[i]       status[i](=1)

TimeOffsets_MemEven

#Module       Chip       Chn       MemOffsetEven[i]       MemOffsetEvenErr[i]       status[i](=1)






  • No labels