Not all Library Components have the same minimum standard for the Components here are the requirments for creating and checking of Components before or in review process.
Requirements for Symbols
- The most upper left pin must be located on the zero piont
- +VCC Pins should be located on the lower left Corner
- -VCC or GND Pins should be located on the lower right corner
- One exception exist to Leveltranslator ICs: VCCA and VCCB should be located on the Top and Group the Pins referenced to this Voltage under it.
- If VCC and GND are to much add it to a sub-part
- Don't place pins on the top or bottom of the symbol
- Don't use a rectangle with transparent enabled
- Group Pins by Function
- Mark Low active pins with a # at the end of the name
- Designator Naming should follow Component Designator Reference table
- Item ID Naming should follow this scheme: SYM-[Group Shortname (like IC,RF ... etc)]_[sequential number]
- The Name should be [ManufacturerNameAbbreviation]_[ManufacturerPartNumber]
- The electrical type of a pin should be set properly
- The Pinlength should be 200mil (if Pinnumber is to long use 300mil)
- The Symbol must be drawn in 50/100mil grid (drawing/additional infos could be made in 10mil grid)
- One example for a symbol:
- Courtyard is needed on Layer 15, in nominal Footprints the distance between copper and Line shall be at least 0.2mm. Line width is 0.05mm. A cross shall be located in the middle of the component.
- The reference point must be at the center of a component. At THT-Header the reference point is located at PIN 1.
- On Layer 5 shall be placed Assembly Notes ( for example marks for PCB edges or marks for LEDs etc.)
- On Layer 11 shall be the Componentoutline with a Indicator of Pin1
- On Layer 13 shall be a 3D-Body
- On Layer 30 shall be the text .Designator
- On Layer 31 shall be the text .Comment
- Top Overlay min line width for N Footprints is 0.12mm, min distance copper to overlay 0.12mm. For L-Footprints the width and distance is 0.1mm
Pin 1 shall be marked in Overlay. Use a triangle, a line under Pin1 or both.
Zero Orientation shall follow IEC 61188-7 “Level B” (IPC 7351C - Level B) with most Pin 1 in Lower Left Corner
- Pads should be rounded rectangle, except thermal pads under BTC's they must be rectangle
- Thermal Pads under BTC's shall have a Paste Pattern with around 50% paste in respect to the complete pad
- This pattern shall also be defined with a corresponding solder mask (see example below)
- Follow Footprint naming convention for the Name
- The Item ID should be PCC-[ManufacturerNameAbbreviation or Footprint Group Shortname (like QFN, SOIC ... etc)]_[sequential number]