Problem

Not all Library Components have the same minimum standard for the Components here are the requirments for creating and checking of Components before or in review process.

Requirements for Symbols

  1. The most upper left pin must be located on the zero piont
  2. +VCC Pins should be located on the lower left Corner
  3. -VCC or GND Pins should be located on the lower right corner
  4. One exception exist to Leveltranslator ICs: VCCA and VCCB should be located on the Top and Group the Pins referenced to this Voltage under it.
  5. If VCC and GND are to much add it to a sub-part
  6. Don't place pins on the top or bottom of the symbol
  7. Don't use a rectangle with transparent enabled
  8. Group Pins by Function
  9. Mark Low active pins with a # at the end of the name
  10. Designator Naming should follow Component Designator Reference table
  11. Item ID Naming should follow this scheme: SYM-[ManufacturerNameAbbreviation]_[ManufacturerPartNumber]
  12. The Name should be [ManufacturerNameAbbreviation]_[ManufacturerPartNumber]
  13. The electrical type of a pin should be set properly
  14. The Pinlength should be 200mil (if Pinnumber is to long use 300mil)
  15. The Symbol must be drawn in 50/100mil grid (drawing/additional infos could be made in 10mil grid)
  16. One example for a symbol:

Requirements Footprints

  1. Courtyard is needed on Layer 15, in nominal Footprints the distance between copper and Line shall be at least 0.2mm. Line width is 0.05mm. A cross shall be located in the middle of the component.
  2. The reference point must be at the center of a component. At THT-Header the reference point is located at PIN 1.
  3. On Layer 5 shall be placed Assembly Notes ( for example marks for PCB edges or marks for LEDs etc.)
  4. On Layer 11 shall be the Componentoutline with a Indicator of Pin1
  5. On Layer 13 shall be a 3D-Body
  6. On Layer 30 shall be the text .Designator
  7. On Layer 31 shall be the text .Comment
  8. Top Overlay min line width is 0.12mm, min distance copper to overlay 0.12mm
  9. Zero Orientation shall follow IEC 61188-7 “Level B” (IPC 7351C - Level B) with most Pin 1 in Lower Left Corner
  10. One example:
  11. Pads should be rounded rectangle, except thermal pads under BTC's they must be rectangle
  12. Thermal Pads under BTC's shall have a Paste Pattern with around 50% paste in respect to the complete pad
  13. This pattern shall also be defined with a corresponding solder mask (see example below)
  14. Follow Footprint naming convention for the Name
  15. The Item ID should be PCC-[ManufacturerNameAbbreviation or Footprint Group Shortname (like QFN, SOIC ... etc)]_[sequential number]

Requirements Components

  1. Use component templates