Page tree


Firmware

firmware_v3.3_TB1904.zip

Data Format

FPGA data package (v1)




Sensor data package

Command format

RBCP address table:  Firmware V3.3

RBCP AddressModeResetReigister
0x00000000W0x00Command Register
0x10000001RW0x00ALPIDE ChipID under Test
0x10000002RW0x00ALPIDE Register Address to Read or Write[15:8]
0x10000003RW0x00ALPIDE Register Address to Read or Write[7:0]
0x10000004RW0x00Data Wrote to ALPIDE Register [15:8]
0x10000005RW0x00Data Wrote to ALPIDE Register [7:0]
0x10000006RW0x00Broadcast OPCODE
0x10000007RW0x00Trigger Delay in Step of 25 ns[15:8]
0x10000008RW0x00Trigger Delay in Step of 25 ns[7:0]
0x10000009RW0x00Reserved. Not used now.
0x1000000aRW0x00Reserved. Not used now.
0x1000000bRW0x00Gap of Internal Trigger in Step of 5μs[15:8]
0x1000000cRW0x14Gap of Internal Trigger in Step of 5μs[7:0]
0x1000000dR0x00Succeed Read Counts
0x1000000eR0x00Data Read from ALPIDE Register[15:8]
0x1000000fR0x00

Data Read from ALPIDE Register[7:0]

0x10000010RW0x00FPGA Working Mode
0xFFFFFC18RW0xc0SiTCP IP_address_base[31:24]
0xFFFFFC19RW0xa8SiTCP IP_address_base[23:16]
0xFFFFFC1aRW0x0aSiTCP IP_address_base[15:8]
0xFFFFFC1bRW0x10SiTCP IP_address_base[7:0]
0xFFFFFCFFW
SiTCP IP EEPROM  write enable (write Zero to it, and then write IP_address_base)



0x00000000 Command Register
The command register is a special register allowing the execution of internal operations or sequences. The valid command codes are list as below.
0xFF: Reset the DAQ System including all the registers. The SiTCP would need 3-4 seconds to reconnect.
0x50: Broadcast command in the Broadcast OPCODE register to ALPIDE chip.
0x9C: Write data in Data Wrote to ALPIDE register at ALPIDE Register Address.
0x4E: Read data from ALPIDE register at ALPIDE Register Address and store in Data Read.

0x10000001 ALPIDE ChipID
ChipID of the ALPIDE chip under test. Mismatch of the ChipID would make ALPIDE register read/write fail.

0x10000002-3 ALPIDE Register Address
These registers store the 16-bit address of the ALPIDE register to be read/wrote in the next read/write operation.

0x10000004-5 ALPIDE Register Write Data
These registers store the 16-bit data to be wrote to ALPIDE register in the next write operation.

0x10000006 ALPIDE Broadcast OPCODE
This register stores the OPCODE to broadcast to the ALPIDE DCTRL bus.

0x10000007-8 Trigger Delay
Controls the delay from external trigger to DAQ sending trigger to ALPIDE. Value n gives a delay of n clock cycles (minimum 0 and maximum 65535 cycles i.e. from 0 to ~1638 us assuming a clock period of 25 ns).

0x1000000B-C Internal Trigger Cycle Time
Controls the frequency of the internal trigger in step of 5μs. The cycle time has a minimum value of 1. A 0 would be reset to 1 if wrote to this register.

0x1000000D Read Counts
A counter of succeed ALPIDE register reading process.

0x1000000E-F ALPIDE Register Read Data
These registers store the 16-bit data read back from the ALPIDE register.

0x10000010 FPGA Mode
This register controls the working mode of the DAQ system.
Bit 7:2 - Not used.
Bit 1 - 1: Internal trigger mode. 0: External trigger mode.
Bit 0 - 1: ALPIDE samples frame data continuously. 0: ALPIDE IDLE.

0xFFFFFC18-B  EEPROM IP address base

The base IP address is stored in EEPROM.  The run-time ip address[7:8] is  the sum of  value in 0xFFFFFC  and onboard switch state.

0xFFFFFCFF   EEPROM IP address write enable.

Only after a Zero  is written to this,  the EEPROM IP address will be writable.





  • No labels